Date

Topics

Assignments

Thursday, 01/04

Introduction

Machine Learning in Systems Research (Leo)

Required reading for 01/09:

·      A probabilistic graphical model-based approach for minimizing energy under performance constraints. N Mishra, H Zhang, JD Lafferty, H Hoffmann - ACM SIGPLAN Notices

·      Recognizing Functions in Binaries with Neural Networks. ECR Shin, D Song, R Moazzezi - USENIX Security Symposium, 2015

·      Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications. G Li, SKS Hari, M Sullivan, T Tsai, K Pattabiraman - SC, 2017

Required reading for 1/11:

·      Quantitative evaluation of soft error injection techniques for robust system design. H Cho, S Mirkhani, CY Cher, JA Abraham

·      Relyzer: Exploiting application-level fault equivalence to analyze application resiliency to transient faults. SKS Hari, SV Adve - ACM SIGPLAN 2012

Optional reading:

·      Configurable detection of SDC-causing errors in programs. Q Lu, G Li, K Pattabiraman - TECS, 2017

·      AutoMOMML: Automatic Multi-objective Modeling with Machine Learning. P Balaprakash, A Tiwari, SM Wild, L Carrington

·      Machine learning-based anomaly detection for post-silicon bug diagnosis. Andrew DeOrio ;  Qingkun Li ;  Matthew Burgess ;  Valeria Bertacco - DATE 2013

Tuesday, 01/09

Machine Learning in Systems Research (Leo)

Thursday, 01/11

Tuesday, 01/16

Photonic Interconnects and Logic (Reza)

Session 1: Overview and Background of Optical Network-on-chip/package

Optional Reading:

1. On-Chip Photonic Interconnects: A Computer Architect's Perspective. Christopher J. Nitta, Matthew K. Farrens, and Venkatesh Akella. - Morgan & Claypool Publishers, 2013

2.  On-Chip Networks, second edition. Natalie Enright Jerger, Tushar Krishna, and Li-Shiuan Peh. - Morgan & Claypool Publishers, 2017

Session 2: On-chip Optical Interconnects

Required Reading:

1. Corona: System Implications of Emerging Nanophotonic Technology. Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan Binkert, Raymond G. Beausoleil, and Jung Ho Ahn. - ISCA '08

2. Firefly: illuminating future network-on-chip with nanophotonics. Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, and Alok Choudhary - ISCA '09

Optional Reading:

1. DCAF - A directly connected arbitration-free photonic crossbar for energy-efficient high performance computing. Christopher J. Nitta, Matthew K. Farrens, and Venkatesh Akella. - IEEE International Parallel and Distributed Processing Symposium, pages 1144–1155, May 2012c

2. Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors. A. Shacham, K. Bergman and L. P. Carloni. - IEEE Transactions on Computers, vol. 57, no. 9, pp. 1246-1260, Sept. 2008

3. Silicon-photonic clos networks for global on-chip communication. Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, and Vladimir Stojanovic. - NOCS '09

Session 3: Datacenter Networks and Optical Logic

Required Reading:

1. c-Through: part-time optics in data centers. Guohui Wang, David G. Andersen, Michael Kaminsky, Konstantina Papagiannaki, T.S. Eugene Ng, Michael Kozuch, and Michael Ryan. - SIGCOMM '10

2. Helios: a hybrid electrical/optical switch architecture for modular data centers. Nathan Farrington, George Porter, Sivasankar Radhakrishnan, Hamid Hajabdolali Bazzaz, Vikram Subramanya, Yeshaiahu Fainman, George Papen, and Amin Vahdat. - SIGCOMM '10

3. DOS: a scalable optical switch for datacenters. Xiaohui Ye, Yawei Yin, S. J. B. Yoo, Paul Mejia, Roberto Proietti, and Venkatesh Akella. - ANCS '10

Optional Reading:

1. Hi-LION: hierarchical large-scale interconnection optical network with AWGRs. Z. Cao, R. Proietti, S.J.B. Yoo. - J. Opt. Commun. Netw. 7(1), A97–A105 (2015)

2. The Data Vortex optical packet switched interconnection network. O. Liboiron-Ladouceur, A. Shacham, B.A. Small, B.G. Lee, H. Wang, C.P. Lai, A. Biberman, K. Bergman. - J. Lightw. Technol. 26(13), 1777–1789 (2008)

Thursday, 01/18

Tuesday, 01/23

Thursday,01/25

Tuesday, 01/30

Heterogeneous Computing (Kevin)

--- Day 1: Heterogeneity in Computing Systems ---

Optional:

Improving MapReduce Performance in Heterogeneous Environments. Matei Zaharia,

Andy Konwinski, Anthony D. Joseph, Randy Katz, Ion Stoica. OSDI 2008.

A Berkeley View of Systems Challenges for AI. Ion Stoica, Dawn Song, Raluca Popa, David Patterson, Michael Mahoney, Randy Katz, Anthony Joseph, Michael Jordan, Joseph Hellerstein, Joseph Gonzalez, Ken Goldberg, Ali Ghodsi, David Culler, Pieter Abbeel. 2017.

--- Day 2: Heterogeneous multi-core (mechanisms) ---

Required:

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. Rakesh Kumar, Keith Farkas, Norman Jouppi, Parthasarathy Ranganathan, Dean Tullsen. MICRO 2003.

Core Architecture Optimization for Heterogeneous Chip Multiprocessors. Rakesh Kumar, Dean Tullsen, Norman Jouppi. 2006.

--- Day 3 Heterogeneous multi-core (policies) ---

Required:

Accelerating Critical Section Execution with Asymmetric Multi-Core

Architectures. M. Aater Suleman, Onur Mutlu, Moinuddin Qureshi, Yale Patt. ASPLOS 2009.

Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE). Kenzo Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narvarez, Joel Elmer. ISCA 2012.

Optional:

Operating System Support for Overlapping-ISA Heterogeneous Multi-core

Architectures. Tong Li, Rob Knauerhase, David Koufaty, Dheeraj Reddy, Scott Hahn. 2010.

Thursday, 02/01

Tuesday, 02/06

No Class

Thursday, 02/08

Heterogeneous Computing (Kevin)

Tuesday, 2/13

Thursday, 02/15

Minimizing Energy with Constraints (Aji)

First meeting: GPU Energy Saving Strategy

Required:

1. O. Kayıran, A. Jog, M. T. Kandemir and C. R. Das, "Neither more nor less: Optimizing thread-level parallelism for GPGPUs," Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, 2013, pp. 157-166.
2. A. Majumdar, L. Piga, I. Paul, J. L. Greathouse, W. Huang and D. H. Albonesi, "Dynamic GPGPU Power Management Using Adaptive Model Predictive Control," 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, 2017, pp. 613-624.
3. A. Sethia and S. Mahlke, "Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution," 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, Cambridge, 2014, pp. 647-658.
4. M. H. Santriaji and H. Hoffmann, "GRAPE: Minimizing energy for GPU applications with performance requirements," 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Taipei, 2016, pp. 1-13.

Second meeting: Minimizing Energy with Constraints.

Required:

1. D. H. K. Kim, C. Imes and H. Hoffmann, "Racing and Pacing to Idle: Theoretical and Empirical Analysis of Energy Optimization Heuristics," 2015 IEEE 3rd International Conference on Cyber-Physical Systems, Networks, and Applications, Hong Kong, 2015, pp. 78-85.
2. Padmanabhan Pillai and Kang G. Shin. 2001. Real-time dynamic voltage scaling for low-power embedded operating systems. In Proceedings of the eighteenth ACM symposium on Operating systems principles (SOSP '01). ACM, New York, NY, USA, 89-102. 
3. Martina Maggio, Alessandro Vittorio Papadopoulos, Antonio Filieri, and Henry Hoffmann. 2017. Automated control of multiple software goals using multiple actuators. In Proceedings of the 2017 11th Joint Meeting on Foundations of Software Engineering (ESEC/FSE 2017). ACM, New York, NY, USA, 373-384.
4. A. Lukefahr et al., "Composite Cores: Pushing Heterogeneity Into a Core," 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, Vancouver, BC, 2012, pp. 317-328.

Third meeting: Toward a Self-Aware and Self Behave Computer System

Tuesday, 02/20

Thursday, 02/22

Tuesday, 02/27

Cross-Layer System Design (Henry)

Session 1:

1.  Cheng, E., et al., “CLEAR: cross-layer exploration for architecting resilience - combining hardware and software techniques to tolerate soft errors in processor cores,” ACM/EDAC/IEEE Design Automation Conf., 2016

2. Hans-Joachim Wunderlich, Martin Radetzki, Multi-Layer Test and Diagnosis for Dependable NoCs, NOCS '15

3. M. S. Golanbari, A cross-layer approach for resiliency and energy efficiency in near threshold computing, ICCAD '16

4. Sun Z, et al. Cross-Layer Racetrack Memory Design for Ultra High Density and Low Power Consumption, DAC 13

Optional:

1. Rafael Kioji Vivas Maeda, Frank Sill Torres, CLEVER: Cross-Layer Error Verification, Evaluation and Reporting, SBCCI '14.

2. Widow, B. et al, An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation, TACO 2016.

3. Gupta , M., et al. Cross-layer system resilience at affordable power, 2014 IEEE International Reliability Physics Symposium.

4. V. Carrascal, et al, DYNAMO: A Cross-Layer Framework for End-to-End QoS and Energy Optimization in Mobile Handheld Devices, QShine 08.

Session 2:

1. Vinay K. Chippa, Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency, DAC10

2.  Muhammad Shafique, et al, Cross-Layer Approximate Computing: From Logic to Architectures, DAC16.

3. John Sartori, et al, Stochastic Computing: Embracing Errors in Architecture and Design of Processors and Applications, CASES 11

Thursday, 03/01

Tuesday, 03/06

Tuesday, 03/13

Final technical report due