CMSC 22200 Computer Architecture

Autumn 2017

 

Course Hours and Location:

Tuesday and Thursday, 2:00pm-3:20pm, Ry 251

 

Lab Hours and Location:

Wednesday, CSIL4 
(Attendance is not required; you may attend any of the lab sessions)

                                                Session 1: 2:30pm – 3:50pm

                                                Session 2: 4:00pm – 5:20pm

                                                Session 3: 5:30pm – 6:50pm

 

Instructor

Yanjing Li (yanjingl@uchicago.edu)

  Office Hours: Tuesdays and Thursdays, after lecture; or by appointment

 

Teaching Assistant

Xin-Chuan Ryan Wu (xinchuan@uchicago.edu)

  Office Hours: Monday and Wednesday 7pm - 9pm CSIL4;
  Lab Review Session: Friday 4:30pm - 5:30pm, location:Ry276

 

Course Description

Computing systems have advanced rapidly and transformed every aspect of our lives for the last few decades, and innovations in computer architecture is a key enabler. Residing in the middle of the system design layers, computer architecture interacts with both the software stack (e.g., operating systems and applications) and hardware technologies (e.g., logic gates, interconnects, and memories) to enable efficient computing with unprecedented capabilities. In this course, students will learn the fundamental principles, techniques, and tradeoffs in designing the hardware/software interface and hardware components to create a computing system that meets functional, performance, energy, cost, and other specific goals. Example topics include instruction set architecture (ISA), pipelining, memory hierarchies, input/output, and multi-core designs. In addition, we will discuss advanced topics regarding recent research and trends. This course also includes hands-on labs, where students will enhance their learning by implementing a modern microprocessor in a C simulator.

 

Prerequisites

Students are expected to be able to program in C and have basic computer systems background (e.g., have taken CMSC 15400)

 

Grading

Lab project: 50%

Exam I: 25%

Exam II: 25%

 

Textbook

 Computer Organization and Design: ARM Edition, Patterson and Hennessy (Required)

 

Exams

There are two exams in class, on 11/02 (Thursday) and 11/28 (Tuesday).

There are no make-up exams, except for extenuating situations, e.g., illnesses requiring hospitalization, a death in the immediate family (siblings, parents, grandparents). Please contact me immediately if you think you have a legitimate reason to be absent.

 

Labs

You are not required to attend lab, and no instructor or TA will be present. However, we encourage you to take advantage of the reserved time slot and resources to work on lab assignments.

 

Lab Submission

All lab assignments are posted online at the class website.

You will be working in groups of 2 for all lab assignments, and we require only one copy of the work to be turned in from each group.

Watch out - they build on each other. Make sure you start early so you can complete them before the deadline. Otherwise, you will stay behind for the next assignment.

 

Late Policy

All lab assignments are due at 11:59pm on the due date. You may turn in lab assignments up to 24 hours late for a 10% penalty and 24-48 hours late for a 20% penalty. After two days past the due date, they will not be accepted.

 

General Information on Lab Assignments, Use of Reference Simulators, etc.

First, the purpose of the lab assignments is to enhance your understanding of computer architecture concepts. We always try to be as specific as possible in the write-ups; however, there can still be multiple valid implementations. You are free to implement the processor simulator based on your understanding as long as they satisfy the lab requirements. Furthermore, we are very reasonable when it comes to grading, and if you can show us that you truly understand course materials, we will not take off points even if there are a few *small* discrepancies between your implementation and the write-up.

Second, we provide the reference simulators just to help with understanding the requirements of the lab and testing your code. However, if your results do not match ours exactly, it doesn't necessarily mean that you implementation is incorrect (and, of course, you won't lose points if your implementation is correct). You should use good judgment when referring to the results of the reference simulators, and you're always welcome to ask clarification questions.

Finally, we only guarantee that our reference simulators are correct for the test cases provided.

 

Piazza

Important announcements will be made via Piazza. It will also be used for you to post questions. Do not post code publicly on Piazza. Check your code into svn or use private posts instead.

You need to sign up for the class. Follow this link: piazza.com/uchicago/fall2017/cmsc222001.

 

Note on academic dishonesty and plagiarism

Cooperative work is an important part of learning; you are encouraged to study together, discuss the lectures, laboratory concepts and computer architecture issues.

 

For lab assignments, you will be working in groups of 2, and you may discuss anything you want with your partner. If you get stuck, it's important that you seek out the proper help - always go the TAs or myself first. Be careful that you DO NOT,

-- copy work (even one line) from another group's assignment or file.
-- copy work (even one line) from a published source without credit (and permission from instructor).
-- lend another group your assignment.                                                                              
-- look at another group?s working code to fix your problem
-- e-mail or transfer any of your files to another student who?s not your lab partner.

If you have a bug, you may ask a student who has gotten farther in the lab to help you find your mistake.  You may not look at his/her project if that student is not your lab partner.

If you violate these rules, you will receive an F grade.

 

Acknowledgements

Prof. Fred Chong (class materials from CS154 in UCSB)

Dr. Diana Franklin (class materials from CS154 in UCSB)

Prof. James Hoe (class materials from 18447 in CMU)

Prof. Onur Mutlu (class materials from 18447 in CMU)

 

 

Course Topics and Schedule (subject to change)

 

Date

Topics

Exams and Assignments

Tuesday, 09/26

 Introduction and basic concepts

 Lab0 Write up
 Lab0 Source file
 SVN cheat sheet

 (svn setup, not graded)

Thursday, 09/28

 Introduction to ISA

 

Readings: P&H Chapter 2; Appendix D (optional)

Lab1 Write up
Lab1 Source file
Lab1 reference simulator
Lab1 inputs

Tuesday, 10/03

 ISA and Introduction to Microarchitecture

 

Readings: P&H 4.1-4.4; Appendix A

 

Thursday, 10/05

 Single-Cycle Processor; Pipelining

 

Readings: P&H 4.5-4.6


Tuesday, 10/10

 Pipelining Discussions, Data Dependency Handling

 

Readings: P&H 4.7

Lab1 due, Lab2 out
Lab2 Write up
Lab2 Source file
Lab2 ref sim v2 Lab2_inputs

Thursday, 10/12

 Data and Control Dependency Handling

 

Tuesday, 10/17

 Branch prediction

 

Readings: P&H 4.8; [McFarling DEC WRL TR 93] (optional)

 

Thursday,10/19

(Make-up class: 10/20)

 Exceptions; OOO: Motivation, Basci Idea, Tomasulo's Algorithm

 

Readings: P&H 4.10

Lab3 out
Lab3 Write up
Lab3 Source file
Lab3 reference simulator
Lab3 inputs

Tuesday, 10/24

 OOO (Reorder buffer, Memory Disambiguation, Discussions) and SIMD

Lab2 due

Thursday, 10/26

 Vector Processors, VLIW, Memory Hierarchy, and caches

 

Readings: P&H 6.3, 5.1-5.3


Tuesday, 10/31

(Make-up class: 10/27)

 

Exam I review

 

Thursday, 11/02

 

 Exam I (in class)
 Practice Problems (lectures 1-7)

 Practice Problems part2 (lectures 1-9)

Tuesday, 11/07

 Caches, basics and advanced topics

 

Thursday, 11/09

 Virtual Memory

Readings: P&H 5.1-5.4

Lab3 due, Lab4 out

Lab4 Write up
Lab4 source file
Lab4 reference simulator

Tuesday, 11/14

 

Main Memory, DRAM

 

Thursday, 11/16

 

Multi-Core

 

Readings: P&H 6.1, 6.2, 6.5, 6.7


Tuesday, 11/21

 Exam II Review

Lab4 due, Lab5 (extra credit) out

Lab5 Write up

 

Thursday, 11/23

No class (Thanksgiving)


Tuesday, 11/28


Exam II (in class)
 Practice Problems (part1, cache and memory)

 Practice Problems part2

Tuesday, 12/5

 

  Lab5 due